1. Technical Field
Exemplary embodiments are directed to semiconductor circuit designs, and more particularly, to methods of performing static timing analysis for integrated circuits.
2. Discussion of the Related Art
In designing an integrated circuit, such as a system-on-chip (SoC), static timing analysis (STA) is performed to analyze timings of the designed integrated circuit. This static timing analysis may reflect process variations in the step of designing the integrated circuit, thereby improving a yield of the integrated circuit. A widely used method of static timing analysis is a statistical static timing analysis (SSTA) that statistically reflects a probability distribution of timing or an operation speed of the integrated circuit. However, SSTA requires a long time for a library development and/or a static timing analysis, and thus is more or less unsuitable for a modern SoC development that needs a short time-to-market. Recently, a parameterized on-chip-variation (POCV) static timing analysis has been developed to reduce the time required for library development and/or the time required for static timing analysis. However, this POCV static timing analysis does not accurately reflect global variations in the timing analysis.